EPI integrality on source/drain region of FinFET
Abstract:
A method for manufacturing a semiconductor device includes providing a substrate structure including a semiconductor fin on a substrate, and a trench isolation structure surrounding the fin and having an upper surface flush with an upper surface of the fin and including first and second trench isolation portions on opposite sides of the fin along the fin longitudinal direction, and third and fourth trench isolation portions on distal ends of the fin along a second direction intersecting the longitudinal direction; forming a patterned first hardmask layer having an opening exposing an upper surface of the third and fourth trench isolation portions; and forming a first insulator layer filling the opening to form an insulating portion including a portion of the first insulator layer in the opening and a portion of the trench isolation structure below the portion of the first insulator layer in the opening.
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