Invention Grant
- Patent Title: Reduced resistance source and drain extensions in vertical field effect transistors
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Application No.: US15695319Application Date: 2017-09-05
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Publication No.: US10332995B2Publication Date: 2019-06-25
- Inventor: Peng Xu , Chun W. Yeung , Chen Zhang
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/08 ; H01L29/78 ; H01L29/66 ; H01L21/311

Abstract:
Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.
Public/Granted literature
- US20180197989A1 REDUCED RESISTANCE SOURCE AND DRAIN EXTENSIONS IN VERTICAL FIELD EFFECT TRANSISTORS Public/Granted day:2018-07-12
Information query
IPC分类: