A signal receiving apparatus includes a clock and data recovery (CDR) circuit, a first sampler, and at least one deskew circuit. The CDR circuit receives a first signal through a first lane of the signal receiving apparatus and decodes the first signal to extract a first clock signal from the first signal. The CDR circuit provides the first clock signal to the first sampler and the least one deskew circuit. The first sampler receives the first signal through the first lane of the signal receiving apparatus. The first sampler samples the first signal based on the first clock signal to generate a first output signal. The at least one deskew circuit receives a second signal through at least one second lane of the signal receiving apparatus and adjusts a phase skew between the first clock signal and the second signal so as to generate a second output signal.