Invention Grant
- Patent Title: Calibration pattern and duty-cycle distortion correction for clock data recovery in a multi-wire, multi-phase interface
-
Application No.: US15971016Application Date: 2018-05-04
-
Publication No.: US10333690B1Publication Date: 2019-06-25
- Inventor: Ying Duan , Abhay Dixit , Shih-Wei Chou , Chulkyu Lee
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: H04L7/033
- IPC: H04L7/033 ; H04L7/00 ; G09G5/00 ; H04L25/49

Abstract:
Methods, apparatus, and systems for calibration and correction of data communications over a multi-wire, multi-phase interface are disclosed. In particular, calibration is provided for data communication devices coupled to a 3-line interface. The calibration includes generating and transmitting a calibration pattern on the 3-line interface, where the generation of the pattern includes toggling two of three interface lines from one voltage level to another voltage level over a predetermined time interval. Furthermore, the generation of the pattern includes maintaining a remaining third interface line at a common mode voltage level over the predetermined time interval, wherein only a single transition occurs for the predetermined time interval. Calibration data may then be derived in a receiver device using the transmitted calibration pattern.
Information query