Invention Grant
- Patent Title: System and method for high voltage stress testing plurality of parallel units
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Application No.: US14950922Application Date: 2015-11-24
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Publication No.: US10338131B2Publication Date: 2019-07-02
- Inventor: Joseph Milton Yehle , Xu Gao , L Rene′ Graves
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Ronald O. Neerings; Charles A. Brill; Frank D. Cimino
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G01R31/02 ; G01R31/28 ; H01L21/44 ; H01L21/66 ; G01R31/12
Abstract:
A system has a chip mounting board and a docking board. The chip mounting board can be loaded with test samples in a low voltage environment and can then be transported to a high voltage environment. The chip mounting board can be connected to the docking board and allows high voltage testing of multiple samples in parallel. The chip mounting board can then be disconnected from the docking board and transported back to a low voltage environment to unload the tested samples.
Public/Granted literature
- US20170146565A1 SYSTEM AND METHOD FOR HIGH VOLTAGE STRESS TESTING PLURALITY OF PARALLEL UNITS Public/Granted day:2017-05-25
Information query
