Invention Grant
- Patent Title: Integrated circuit with low power scan system
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Application No.: US15365890Application Date: 2016-11-30
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Publication No.: US10338136B2Publication Date: 2019-07-02
- Inventor: Ling Wang , Wanggen Zhang , Wei Zhang
- Applicant: NXP USA, INC.
- Applicant Address: US TX Austin
- Assignee: NXP USA, INC.
- Current Assignee: NXP USA, INC.
- Current Assignee Address: US TX Austin
- Agent Charles E. Bergere
- Priority: CN201610754723 20160829
- Main IPC: G01R31/3177
- IPC: G01R31/3177 ; G01R31/317 ; G01R31/3185 ; G01R31/34

Abstract:
An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.
Public/Granted literature
- US20180059178A1 INTEGRATED CIRCUIT WITH LOW POWER SCAN SYSTEM Public/Granted day:2018-03-01
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