A buffer stage includes a first transistor having a control terminal connected to an output terminal of an operational amplifier and a second transistor connected in series to a main energization path of the first transistor. An overcurrent controlling circuit is configured to apply an output voltage of the operational amplifier to the control terminal of the first transistor and allow a normal operation of the first transistor when an energization current of a main energization path of an output transistor detected by an overcurrent detection transistor is less than a predetermined value, and is configured to control the output voltage of the operational amplifier to a predetermined control voltage according to a current flowing in a main energization path of the overcurrent detection transistor when the energization current of the main energization path of the output transistor is equal to or greater than the predetermined value.