Invention Grant
- Patent Title: System and method to match vectors using mask and count
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Application No.: US15853707Application Date: 2017-12-22
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Publication No.: US10339043B1Publication Date: 2019-07-02
- Inventor: Michael J Miller
- Applicant: MoSys, Inc.
- Applicant Address: US CA San Jose
- Assignee: MoSys, Inc.
- Current Assignee: MoSys, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H04L12/745
- IPC: H04L12/745 ; G06F12/02 ; H04L29/12

Abstract:
An apparatus, system, and method is described for calculating a composite index into a customizable hybrid address space that is at least partially compressed to locate a longest prefix match (“LPM”) of a prefix string comprised of a plurality of multi-bit strides (“MBSs”). The device comprises: a mask-and-count logic for generating a base index into memory for a first MBS whose addresses are not compressed; a logical-shift apparatus that selectively uses a variable portion of the second MBS to generate an offset index from the given base index per an amount the second MBS addresses were actually compressed; and an add logic that adds the base index to the offset index to form the composite index that locates the LPM using a single access into memory. A compressed vector contains compression information of the second MBS in an information density format greater than a single bit to a single address.
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