Invention Grant
- Patent Title: Semiconductor LSI design device and design method
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Application No.: US15622805Application Date: 2017-06-14
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Publication No.: US10339242B2Publication Date: 2019-07-02
- Inventor: Takumi Uezono , Tadanobu Toba , Yusuke Kanno , Masahiro Shiraishi , Hideo Harada , Satoshi Nishikawa , Toru Motoya
- Applicant: Hitachi, Ltd.
- Applicant Address: JP Tokyo
- Assignee: Hitachi, Ltd.
- Current Assignee: Hitachi, Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Crowell & Moring LLP
- Priority: JP2016-118531 20160615
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.
Public/Granted literature
- US20170364610A1 Semiconductor LSI Design Device and Design Method Public/Granted day:2017-12-21
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