Invention Grant
- Patent Title: Semiconductor package and method of manufacturing the same
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Application No.: US15700422Application Date: 2017-09-11
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Publication No.: US10340207B2Publication Date: 2019-07-02
- Inventor: Yoshihisa Imori , Kenji Yamada
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Priority: JP2017-033621 20170224
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/495
Abstract:
According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.
Public/Granted literature
- US20180247883A1 SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2018-08-30
Information query
IPC分类:
