Invention Grant
- Patent Title: ESD protection circuit and method of making the same
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Application No.: US15722744Application Date: 2017-10-02
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Publication No.: US10340266B2Publication Date: 2019-07-02
- Inventor: Yohann Frederic Michel Solaro , Chai Ean Gill , Tsung-Che Tsai
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L27/02
- IPC: H01L27/02 ; H01L29/06 ; H01L29/10 ; H01L29/78
Abstract:
Methods of forming a high voltage ESD GGNMOS using embedded gradual PN junction in the source region and the resulting devices are provided. Embodiments include a device having a substrate including a device region with an ESD protection circuit; a gate over the device region; a source region in the device region having a N+ implant and a P+ implant laterally separated on a first side of the gate; and a drain region in the device region on a second side of the gate, opposite the first.
Public/Granted literature
- US20190103398A1 ESD PROTECTION CIRCUIT AND METHOD OF MAKING THE SAME Public/Granted day:2019-04-04
Information query
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