Invention Grant
- Patent Title: Semiconductor device
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Application No.: US15721901Application Date: 2017-09-30
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Publication No.: US10340291B2Publication Date: 2019-07-02
- Inventor: Nobuo Tsuboi , Yoshiki Yamamoto
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: Shapiro, Gabor and Rosenberger, PLLC
- Priority: JP2016-222054 20161115
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/12 ; G05F1/625 ; H01L29/78 ; H03K17/687 ; H01L27/02 ; H01L29/417 ; H01L21/84

Abstract:
Reliability of a semiconductor device is improved. A p-type MISFET of a thin film SOI type is formed in an SOI substrate including a semiconductor substrate, an insulating layer on the semiconductor substrate, and a semiconductor layer on the insulating layer, and n+-type semiconductor regions which are source and drain region of the p-type MISFET are formed in the semiconductor layer and an epitaxial layer on the semiconductor layer. A semiconductor layer is formed via the insulating layer below the p-type MISFET formed in the n-type well region of the semiconductor substrate. In an n-type tap region which is a power supply region of the n-type well region, a silicide layer is formed on a main surface of the n-type well region without interposing the epitaxial layer therebetween.
Public/Granted literature
- US20180138204A1 SEMICONDUCTOR DEVICE Public/Granted day:2018-05-17
Information query
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