Invention Grant
- Patent Title: Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers
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Application No.: US15804303Application Date: 2017-11-06
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Publication No.: US10340363B2Publication Date: 2019-07-02
- Inventor: Choonghyun Lee , Shogo Mochizuki
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Ryan, Mason & Lewis, LLP
- Agent Vazken Alexanian
- Main IPC: H01L29/08
- IPC: H01L29/08 ; H01L29/66 ; H01L29/78 ; H01L29/417 ; H01L21/8234

Abstract:
A vertical field-effect transistor (FET) device is fabricated with a self-aligned bottom insulating spacer for improved electrostatic control. A semiconductor fin is formed on a semiconductor substrate. A lower source/drain region, which is formed of a first type of epitaxial semiconductor material, is epitaxially grown on a surface of the substrate in contact with a bottom portion of the semiconductor fin. A sacrificial epitaxial semiconductor layer is epitaxially grown on top of the lower source/drain region, wherein the sacrificial epitaxial semiconductor layer is formed of a second type of epitaxial semiconductor material which is different from the first type of epitaxial semiconductor material. The sacrificial epitaxial semiconductor layer is selectively oxidized to form a self-aligned bottom insulating spacer comprising an oxide layer. A gate structure is formed contact with sidewalls of the semiconductor fin. The self-aligned bottom insulating spacer electrically insulates the gate structure from the lower source/drain region.
Public/Granted literature
- US20190140080A1 FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED BOTTOM INSULATING SPACERS Public/Granted day:2019-05-09
Information query
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