A process for fabricating a heterojunction field-effect transistor including a semiconductor structure made up of superposed layers, including: providing on a substrate layer (1) a buffer layer (2), a channel layer (3) and a barrier layer (4), the layers being made of materials having hexagonal crystal structures of the Ga(1-p-q)Al(p)In(q)N type; forming an opening in a dielectric masking layer (5) deposited on the barrier layer; growing by high-temperature epitaxy a semiconductor material (6, 6′) having a hexagonal crystal structure, namely Ga(1-x′-y′)Al(x′)In(y′)N, doped with germanium, on a growth zone defined by the opening formed in the masking layer; and depositing a source or drain contact electrode (15, 16) on the material thus deposited by epitaxy, and a gate electrode (13) in a location outside of the growth zone.