Invention Grant
- Patent Title: Semiconductor constructions, methods of forming vertical memory strings, and methods of forming vertically-stacked structures
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Application No.: US16100003Application Date: 2018-08-09
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Publication No.: US10340393B2Publication Date: 2019-07-02
- Inventor: John D. Hopkins
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L29/66 ; H01L29/792 ; H01L21/336 ; H01L21/28 ; H01L21/02 ; H01L27/11556 ; H01L27/11582 ; H01L29/423 ; H01L29/51
Abstract:
Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.
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