- Patent Title: Soft decision LDPC decoder with improved LLR from neighboring bits
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Application No.: US15702967Application Date: 2017-09-13
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Publication No.: US10340951B2Publication Date: 2019-07-02
- Inventor: David Symons , Paul Hanham , Francesco Giorgio
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: White & Case LLP
- Main IPC: H03M13/11
- IPC: H03M13/11 ; G06F3/06

Abstract:
A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.
Public/Granted literature
- US20190081641A1 Soft Decision LDPC Decoder With Improved LLR From Neighboring Bits Public/Granted day:2019-03-14
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