A memory system may be provided. The memory system may include a memory buffer chip coupled to one or more memory chips. The memory system may include a memory controller configured to control the memory buffer chip to input/output data to/from the one or two or more memory chips. The memory buffer chip may include a first interface configured to transmit/receive a signal to/from the memory controller. The memory buffer chip may include a second interface configured to transmit/receive a signal to/from the memory chip. The memory buffer chip may include a command buffer configured to buffer commands received from the memory controller through the first interface. The memory buffer chip may include a read buffer configured to buffer read data received from the memory chip.