A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.