Invention Grant
- Patent Title: Timer placement optimization
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Application No.: US15791859Application Date: 2017-10-24
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Publication No.: US10346329B2Publication Date: 2019-07-09
- Inventor: Juan M. Casas, Jr. , Nikhil Hegde , Keerthi B. Kumar , Shailaja Mallya
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Lieberman & Brandsdorfer, LLC
- Main IPC: G06F13/24
- IPC: G06F13/24 ; G06F9/00

Abstract:
A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
Public/Granted literature
- US20180276156A1 Timer Placement Optimization Public/Granted day:2018-09-27
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