Invention Grant
- Patent Title: Increasing compression by reducing padding patterns
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Application No.: US15450962Application Date: 2017-03-06
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Publication No.: US10346557B2Publication Date: 2019-07-09
- Inventor: Peter Wohl , John Waicukauski
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Yiding Wu
- Main IPC: G01R31/00
- IPC: G01R31/00 ; G06F17/50 ; G01R31/3183

Abstract:
A method for generating scan-based test patterns for an integrated circuit design includes, in a computer system, generating a number of current interval patterns for the integrated circuit design in a current pattern generation interval. The current interval patterns can be augmented to satisfy observe needs of a previous interval pattern generated in a previous pattern generation interval. Observe needs of the current interval patterns are stored in association with the current interval patterns. The current interval patterns are linked respectively to P streams of test patterns. The current pattern generation interval is subsequent to the previous pattern generation interval. The method includes simulating the current interval patterns to identify observable scan cells in the integrated circuit design, linking the P streams of test patterns into a single stream of test patterns, and storing the single stream of test patterns in a computer readable medium.
Public/Granted literature
- US20180156869A1 Increasing Compression by Reducing Padding Patterns Public/Granted day:2018-06-07
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