Invention Grant
- Patent Title: Placement-based congestion-aware logic restructuring
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Application No.: US15801319Application Date: 2017-11-01
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Publication No.: US10346578B2Publication Date: 2019-07-09
- Inventor: Jagat B. Patel , William Clark Naylor, Jr. , Brent L. Gregory
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.
Public/Granted literature
- US20180121591A1 PLACEMENT-BASED CONGESTION-AWARE LOGIC RESTRUCTURING Public/Granted day:2018-05-03
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