Invention Grant
- Patent Title: Memory layout for preventing reference layer from breaks
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Application No.: US16035868Application Date: 2018-07-16
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Publication No.: US10347302B1Publication Date: 2019-07-09
- Inventor: Cheng-Lung Lin , Wan-Tung Liang
- Applicant: EOREX CORPORATION
- Applicant Address: TW Zhubei, Hsinchu County
- Assignee: EOREX CORPORATION
- Current Assignee: EOREX CORPORATION
- Current Assignee Address: TW Zhubei, Hsinchu County
- Agency: Jackson IPG PLLC
- Agent Demian K. Jackson
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G11C11/21 ; G11C5/14

Abstract:
A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.
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