Discussed are a display device and a method of driving the same. The display device can include a panel in which a pixel is formed in each of a plurality of intersection areas between a plurality of gate lines and a plurality of data lines, a built-in gate driver built into a non-display area of the panel, and configured to include a shift register including a plurality of scan stages which output a scan pulse, and a timing controller configured to generate first to nth clocks, a reset signal, and a start signal. In initial driving of the built-in gate driver, the timing controller continuously supplies a pulse of the reset signal to the plurality of scan stages while a pulse of the nth clock and a pulse of the first clock to a pulse of the (n−1) clock are each output once in a first frame.