Invention Grant
- Patent Title: Memory devices and methods for managing error regions
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Application No.: US15927679Application Date: 2018-03-21
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Publication No.: US10347356B2Publication Date: 2019-07-09
- Inventor: Joe M. Jeddeloh
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H03M13/05
- IPC: H03M13/05 ; G06F12/02 ; G11C29/12 ; G11C29/44 ; G11C29/00 ; H01L25/18 ; H01L27/108 ; G11C5/04 ; H01L27/06 ; H01L27/105

Abstract:
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.
Public/Granted literature
- US20180374557A1 MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS Public/Granted day:2018-12-27
Information query
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