Invention Grant
- Patent Title: Semiconductor structure and fabrication method thereof
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Application No.: US15813420Application Date: 2017-11-15
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Publication No.: US10347496B2Publication Date: 2019-07-09
- Inventor: Xin He
- Applicant: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
- Applicant Address: CN Shanghai CN Beijing
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
- Current Assignee Address: CN Shanghai CN Beijing
- Agency: Anova Law Group, PLLC
- Priority: CN201611089134 20161130
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/306 ; H01L21/28 ; H01L21/3105 ; H01L25/00 ; H01L29/423 ; H01L29/49 ; H01L29/78 ; H01L21/8238 ; H01L21/311 ; H01L29/51 ; H01L21/8234 ; H01L27/092

Abstract:
Semiconductor structures and fabrication methods are provided. The semiconductor structure includes a base including first, second, third, and fourth regions, used for first, second, third, and fourth transistors, respectively. A gate dielectric layer is on the first, second, third and fourth regions of the base. A first material layer is on the gate dielectric layer. A second material layer is on the first material layer above the fourth region. A third material layer is on the first material layer above the third region and on the second material layer above the fourth region. A fourth material layer is on the third material layer above the third and fourth regions and on the first material layer on the second region. The first material layer above the first region is used as a first work function layer for the first transistor.
Public/Granted literature
- US20180151383A1 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF Public/Granted day:2018-05-31
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