Invention Grant
- Patent Title: Method of forming interconnect structure with partial copper plating
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Application No.: US15816973Application Date: 2017-11-17
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Publication No.: US10347530B2Publication Date: 2019-07-09
- Inventor: Ji Guang Zhu , Hai Ting Li
- Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Applicant Address: CN Shanghai CN Ningbo
- Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Current Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION,NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
- Current Assignee Address: CN Shanghai CN Ningbo
- Agency: Anova Law Group, PLLC
- Priority: CN201611054718 20161125
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L21/321 ; H01L21/288 ; H01L23/528

Abstract:
A method for manufacturing an interconnect structure includes providing a substrate structure including a substrate and a dielectric layer on the substrate, the dielectric layer having an opening extending to the substrate. The method further includes forming a mask layer on at least one portion of the dielectric layer, forming a metal layer filling the opening and covering portions of dielectric layer not covered by the mask layer, removing the mask layer, and planarizing the metal layer so that an upper surface of a remaining portion of the metal layer is flush with an upper surface of the dielectric layer. The method can mitigate the warping problems of the substrate associated with the fabrication of the interconnect structure.
Public/Granted literature
- US20180151426A1 METHOD OF FLAT CU FORMING WITH PARTIAL CU PLATING Public/Granted day:2018-05-31
Information query
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