Invention Grant
- Patent Title: Gate cut using selective deposition to prevent oxide loss
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Application No.: US15841887Application Date: 2017-12-14
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Publication No.: US10347540B1Publication Date: 2019-07-09
- Inventor: Andrew M. Greene , Ekmini Anuja De Silva , Siva Kanakasabapathy
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/66 ; H01L21/3213 ; H01L29/78 ; H01L21/28 ; H01L21/8238

Abstract:
Semiconductor devices and methods of forming the same include forming gate stacks across a semiconductor fin, each gate stack having a gate conductor. An interlayer dielectric is formed between the gate stacks. A protective layer is formed on the interlayer dielectric that leaves the gate stacks exposed. The gate conductor of at least one gate stack is etched away. A dielectric liner is formed in a gap left by the etched gate conductor.
Public/Granted literature
- US20190189782A1 GATE CUT USING SELECTIVE DEPOSITION TO PREVENT OXIDE LOSS Public/Granted day:2019-06-20
Information query
IPC分类: