Invention Grant
- Patent Title: Integrated circuit package structure and testing method using the same
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Application No.: US15438894Application Date: 2017-02-22
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Publication No.: US10347548B2Publication Date: 2019-07-09
- Inventor: Yang-Che Chen , Tsung-Te Chou , Chen-Hua Lin , Huang-Wen Tseng , Chwen-Ming Liu
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66 ; G01R31/28 ; H01L23/48 ; H01L23/522 ; H01L23/528 ; H01L21/683 ; H01L21/768 ; H01L23/00 ; H01L25/00 ; H01L25/065 ; H01L23/31 ; H01L21/56
Abstract:
An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
Public/Granted literature
- US20180156865A1 INTEGRATED CIRCUIT PACKAGE STRUCTURE AND TESTING METHOD USING THE SAME Public/Granted day:2018-06-07
Information query
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