Invention Grant
- Patent Title: Method of integrating a copper plating process in a through-substrate-via (TSV) on CMOS wafer
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Application No.: US15615924Application Date: 2017-06-07
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Publication No.: US10347564B2Publication Date: 2019-07-09
- Inventor: Matthieu Lagouge , Qing Zhang , Mohommad Choudhuri , Gul Zeb
- Applicant: NXP USA, Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L21/768 ; H01L21/3213 ; H01L21/288 ; H01L21/3065 ; H01L23/532

Abstract:
A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.
Public/Granted literature
- US20180019187A1 METHOD OF INTEGRATING A COPPER PLATING PROCESS IN A THROUGH-SUBSTRATE-VIA (TSV) ON CMOS WAFER Public/Granted day:2018-01-18
Information query
IPC分类: