Invention Grant
- Patent Title: Method to increase strain in a semiconductor region for forming a channel of the transistor
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Application No.: US15711549Application Date: 2017-09-21
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Publication No.: US10347721B2Publication Date: 2019-07-09
- Inventor: Shay Reboh , Laurent Grenouillet , Raluca Tiron
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1658917 20160922
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/02 ; H01L29/66 ; H01L29/78 ; H01L29/786
Abstract:
There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.
Public/Granted literature
- US20180082837A1 METHOD TO INCREASE STRAIN IN A SEMICONDUCTOR REGION FOR FORMING A CHANNEL OF THE TRANSISTOR Public/Granted day:2018-03-22
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