Invention Grant
- Patent Title: Gapfill improvement
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Application No.: US15991270Application Date: 2018-05-29
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Publication No.: US10347741B1Publication Date: 2019-07-09
- Inventor: Pin-Ju Liang , De-Wei Yu , Yi-Cheng Li , Chien-Hao Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L27/088 ; H01L21/8234 ; H01L21/31 ; H01L21/3105 ; H01L29/49 ; H01L29/66 ; H01L21/02

Abstract:
Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.
Information query
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