Invention Grant
- Patent Title: Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps
-
Application No.: US14026118Application Date: 2013-09-13
-
Publication No.: US10347829B1Publication Date: 2019-07-09
- Inventor: Shan Sun , John Cronin , Tom E. Davenport
- Applicant: Cypress Semiconductor Corporation
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L27/11502
- IPC: H01L27/11502 ; H01L43/14 ; H01L29/51 ; H01L21/28

Abstract:
A method for fabricating a non-volatile, ferroelectric random access memory (F-RAM) device with a reduced number of masking and etching steps is described. In one embodiment, the method includes forming an opening in an insulating layer over a surface of a substrate to expose a portion of the surface, and forming first spacers on sidewalls of the opening. A conductive layer is formed on the portion of the surface exposed in the opening and separated from the first spacers on the sidewalls of the opening by a gap therebetween. A bottom electrode of a ferroelectric capacitor is formed over the conductive layer and in the gap laterally of the conductive layer, a ferroelectric dielectric formed on the bottom electrode between the first spacers, and a top electrode formed on the ferroelectric dielectric.
Information query
IPC分类: