An integrated circuit comprising (i) an array of logic tiles wherein each logic tile is configurable to connect with at least one adjacent logic tile and (ii) a clock mesh fabric including a clock mesh to provide a mesh clock signal to each of the logic tiles of the array of logic tiles. In one embodiment, each logic tile of the array of logic tiles includes (1) distribution and transmission circuitry configurable to provide an associated tile clock to circuitry which performs operations using or based on the associated tile clock, wherein the distribution and transmission circuitry includes circuitry to generate a tile clock signal having a skew which is balanced with respect to the tile clock signals generated by the generation circuitry of each tile, and (2) selection circuitry to responsively output the associated tile clock which corresponds to the mesh clock signal or the tile clock signal.