Invention Grant
- Patent Title: Frequency division correction circuit, reception circuit, and integrated circuit
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Application No.: US15656716Application Date: 2017-07-21
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Publication No.: US10348316B2Publication Date: 2019-07-09
- Inventor: Atsushi Matsuda
- Applicant: SOCIONEXT INC.
- Applicant Address: JP Yokohama
- Assignee: SOCIONEXT INC.
- Current Assignee: SOCIONEXT INC.
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2016-147482 20160727
- Main IPC: H03K23/00
- IPC: H03K23/00 ; H03L7/18 ; H03K7/08 ; H03L7/08 ; H03K5/156 ; H03K23/48 ; H03L7/089 ; H04L7/033
Abstract:
A frequency division correction circuit includes: a first frequency divider configured to perform decimal frequency division on an input signal and output a first frequency division signal and a second frequency division signal which are different from each other in duty ratio; and a corrector configured to generate a first output signal having an intermediate duty ratio between a duty ratio of the first frequency division signal and a duty ratio of the second frequency division signal on the basis of the first frequency division signal and the second frequency division signal.
Public/Granted literature
- US20180034469A1 FREQUENCY DIVISION CORRECTION CIRCUIT, RECEPTION CIRCUIT, AND INTEGRATED CIRCUIT Public/Granted day:2018-02-01
Information query
