- Patent Title: Instruction and logic for parallel multi-step power management flow
-
Application No.: US15374684Application Date: 2016-12-09
-
Publication No.: US10365707B2Publication Date: 2019-07-30
- Inventor: Alexander Gendler , Doron Rajwan , Tal Kuzi , Dean Mulla , Ariel Szapiro , Nir Tell
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/3296 ; G06F1/3206 ; G06F1/324

Abstract:
A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.
Public/Granted literature
- US20180164873A1 INSTRUCTION AND LOGIC FOR PARALLEL MULTI-STEP POWER MANAGEMENT FLOW Public/Granted day:2018-06-14
Information query