Invention Grant
- Patent Title: Memory system controlling interleaving write to memory chips
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Application No.: US15421933Application Date: 2017-02-01
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Publication No.: US10365834B2Publication Date: 2019-07-30
- Inventor: Yoshihisa Kojima , Katsuhiko Ueki
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/06 ; G06F13/16 ; G06F12/02 ; G11C7/10 ; G11C16/04 ; G11C16/10 ; G11C16/34

Abstract:
According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.
Public/Granted literature
- US20170147235A1 MEMORY SYSTEM CONTROLLING INTERLEAVING WRITE TO MEMORY CHIPS Public/Granted day:2017-05-25
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