Invention Grant
- Patent Title: Optimizing DRAM memory based on read-to-write ratio of memory access latency
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Application No.: US15677654Application Date: 2017-08-15
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Publication No.: US10365997B2Publication Date: 2019-07-30
- Inventor: Ahmad Hassan
- Applicant: Hybris AG
- Applicant Address: CH Zug
- Assignee: Hybris AG
- Current Assignee: Hybris AG
- Current Assignee Address: CH Zug
- Agency: Fish & Richardson P.C.
- Main IPC: G06F12/02
- IPC: G06F12/02 ; G11C7/10

Abstract:
Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for receiving a memory access latency value including a time to perform an operation with respect to the memory bank of the plurality of memory banks, receiving a set of operation percentages including an operation percentage for each of a plurality of operations performed on the memory bank, determining a probability associated with the memory access latency value using a mixture of Weibull distributions, described herein, comparing the probability to a threshold probability to provide a comparison, and selectively executing at least one action with respect to the memory bank based on the comparison.
Public/Granted literature
- US20190057023A1 OPTIMIZING DRAM MEMORY BASED ON READ-TO-WRITE RATIO OF MEMORY ACCESS LATENCY Public/Granted day:2019-02-21
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