Semiconductor integrated circuit, timing controller, and display device
Abstract:
A semiconductor integrated circuit connected to another circuit via differential transmission lines of N channels (where N is a natural number), the circuit includes: N pairs of differential output pins each of which is connected to a differential transmission line of a corresponding channel; N differential transmitters each of which is configured to drive a differential transmission line of a corresponding channel; and an abnormality detection circuit configured to detect abnormality in the differential transmission lines. The abnormality detection circuit includes: N amplifiers configured to detect a potential difference between differential transmission lines of corresponding channels; N first comparators each of which is configured to compare an output voltage of a corresponding amplifier with a first threshold voltage; and a logic circuit configured to detect abnormality of a first mode in a differential transmission line of a corresponding channel based on an output from each of the N first comparators.
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