Invention Grant
- Patent Title: Devices with multiple threshold voltages formed on a single wafer using strain in the high-k layer
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Application No.: US15815146Application Date: 2017-11-16
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Publication No.: US10366897B2Publication Date: 2019-07-30
- Inventor: Takashi Ando , Mohit Bajaj , Terence B. Hook , Rajan K. Pandey , Rajesh Sathiyanarayanan
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/02 ; H01L21/3115 ; H01L21/8234 ; H01L21/225 ; H01L27/088 ; H01L29/10 ; H01L29/51 ; H01L29/66 ; H01L29/78 ; H01L21/324 ; H01L29/49
Abstract:
A method for adjusting a threshold voltage includes depositing a strained liner on a gate structure to strain a gate dielectric. A threshold voltage of a transistor is adjusted by controlling an amount of strain in the liner to control an amount of work function (WF) modulating species that diffuse into the gate dielectric in a channel region. The liner is removed.
Public/Granted literature
- US20180096851A1 DEVICES WITH MULTIPLE THRESHOLD VOLTAGES FORMED ON A SINGLE WAFER USING STRAIN IN THE HIGH-K LAYER Public/Granted day:2018-04-05
Information query
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