Invention Grant
- Patent Title: Bottom-up selective dielectric cross-linking to prevent via landing shorts
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Application No.: US15575808Application Date: 2015-06-26
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Publication No.: US10366950B2Publication Date: 2019-07-30
- Inventor: Kevin Lin , Robert Lindsey Bristol , James M. Blackwell , Rami Hourani
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- International Application: PCT/US2015/038167 WO 20150626
- International Announcement: WO2016/209296 WO 20161229
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L21/31 ; H01L21/76 ; H01L23/532 ; H01L23/522 ; H01L21/02 ; H01L21/311 ; H01L21/321 ; H01L21/768

Abstract:
Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
Public/Granted literature
- US20180204797A1 BOTTOM-UP SELECTIVE DIELECTRIC CROSS-LINKING TO PREVENT VIA LANDING SHORTS Public/Granted day:2018-07-19
Information query
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