A quadrature clock divider circuit includes a divide-by-2 circuit having at least one undivided clock input, and generates at least one quadrature clock component and at least one inverted quadrature clock component, each having a 50% duty cycle. A resync circuit has as inputs the at least one undivided clock input, and the uninverted and inverted quadrature clock components. The resync circuit uses the uninverted and inverted quadrature clock components as selectors to generate, from the undivided clock input signals, at least one second quadrature clock component on a first signal path and at least one second inverted quadrature clock component on a second signal path. The first and second signal paths have a first portion in common, and each of the at least one second quadrature clock component and the at least one second inverted quadrature clock component has a second duty cycle percentage other than 50%.