Invention Grant
- Patent Title: Methods and apparatus for read disturb detection based on logical domain
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Application No.: US15394560Application Date: 2016-12-29
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Publication No.: US10372382B2Publication Date: 2019-08-06
- Inventor: Parvaneh Alavi , Hung-min Chang , Haining Liu , Jerry Lo , Hung-Cheng Yeh
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
- Current Assignee Address: US CA San Jose
- Agency: Loza & Loza, LLP
- Agent Gabriel Fitch
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F3/06 ; G11C16/34 ; G11C16/04 ; G11C16/08 ; G11C16/26

Abstract:
Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.
Public/Granted literature
- US20180188981A1 METHODS AND APPARATUS FOR READ DISTURB DETECTION BASED ON LOGICAL DOMAIN Public/Granted day:2018-07-05
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