- Patent Title: Software controlled cache line replacement within a data property dependent cache segment of a cache using a cache segmentation enablement bit and cache segment selection bits
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Application No.: US15417302Application Date: 2017-01-27
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Publication No.: US10372622B2Publication Date: 2019-08-06
- Inventor: Shajith Chandran
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Francis Lammes; Stephen J. Walder, Jr.; David M. Quinn
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/109 ; G06F12/0893 ; G06F12/1009 ; G06F12/12 ; G06F12/127 ; G06F12/0846

Abstract:
Mechanisms are provided, in a data processing system having a processor and a cache subsystem, for providing software controlled cache segmentation and cache segment utilization. The mechanisms segment a cache memory of the cache subsystem such that the cache memory comprises a plurality of cache segments. Each cache segment in the plurality of cache segments is associated with a different data property of data stored in the cache segment. The mechanisms configure software executing on the data processing system to direct cache accesses to one of the cache segments based on a corresponding data property of the cache accesses by the software. The mechanisms process, by the processor, a data access operation from software executing on the processor, based on an identifier of a cache segment in one of an effective address provided by the software or a page table entry corresponding to the effective address provided by the software.
Public/Granted literature
- US20180217938A1 Software Controlled Cache Line Replacement within a Cache Segment Public/Granted day:2018-08-02
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