Invention Grant
- Patent Title: 3D stacked-chip package
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Application No.: US15608466Application Date: 2017-05-30
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Publication No.: US10373885B2Publication Date: 2019-08-06
- Inventor: Chen-Hua Yu , Ming-Fa Chen , Wen-Sen Lu , Wen-Chih Chiou , Wen-Ching Tsai
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L23/00 ; H01L23/538 ; H01L25/00 ; H01L21/768 ; H01L21/56 ; H01L23/36 ; H01L23/48 ; H01L23/498 ; H01L23/522 ; H01L25/065 ; H01L21/311

Abstract:
Disclosed herein is a package comprising a first die having a first redistribution layer (RDL) disposed on a first side of a first substrate and a second die having a second RDL disposed on a first side of a second substrate, with the first RDL bonded to the second RDL. A third die having a third RDL is disposed on a first side of a third substrate, the third die mounted over the second die, with the second die disposed between the first die and the third die. First vias extend through, and are electrically isolated from, the second substrate, with the first vias each contacting a conductive element in the first RDL or the second RDL. Second vias extend through, and are electrically isolated from, the third substrate, with the second vias each contacting a conductive element in the third RDL or one of the first vias.
Public/Granted literature
- US20170263519A1 3D STACKED-CHIP PACKAGE Public/Granted day:2017-09-14
Information query
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