Invention Grant
- Patent Title: OTP cell having a reduced layout area
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Application No.: US15637477Application Date: 2017-06-29
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Publication No.: US10373965B2Publication Date: 2019-08-06
- Inventor: Young Chul Seo , Duk Ju Jeong
- Applicant: MagnaChip Semiconductor, Ltd.
- Applicant Address: KR Cheongju-si
- Assignee: MagnaChip Semiconductor, Ltd.
- Current Assignee: MagnaChip Semiconductor, Ltd.
- Current Assignee Address: KR Cheongju-si
- Agency: NSIP Law
- Priority: KR10-2016-0101304 20160809
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L27/112 ; G11C17/12 ; H01L23/525 ; G11C17/16 ; G11C17/18

Abstract:
An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.
Public/Granted literature
- US20180047736A1 OTP CELL HAVING A REDUCED LAYOUT AREA Public/Granted day:2018-02-15
Information query
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