Invention Grant
- Patent Title: Structure for reduced source and drain contact to gate stack capacitance
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Application No.: US15396796Application Date: 2017-01-02
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Publication No.: US10374046B2Publication Date: 2019-08-06
- Inventor: Carl J Radens , Richard Q Williams
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Jeffrey S LaBaw; Steven J Meyers
- Main IPC: H01L29/41
- IPC: H01L29/41 ; H01L29/417 ; H01L29/06 ; H01L29/78 ; H01L23/535 ; H01L21/027 ; H01L21/306 ; H01L21/683 ; H01L21/768 ; H01L23/528 ; H01L23/532 ; H01L29/45 ; H01L23/522 ; H01L29/423 ; H01L29/786

Abstract:
A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.
Public/Granted literature
- US20170179244A1 STRUCTURE FOR REDUCED SOURCE AND DRAIN CONTACT TO GATE STACK CAPACITANCE Public/Granted day:2017-06-22
Information query
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