Invention Grant
- Patent Title: Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer
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Application No.: US15371315Application Date: 2016-12-07
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Publication No.: US10374574B2Publication Date: 2019-08-06
- Inventor: Joseph Michael Bulger
- Applicant: SKYWORKS SOLUTIONS, INC.
- Applicant Address: US MA Woburn
- Assignee: SKYWORKS SOLUTIONS, INC.
- Current Assignee: SKYWORKS SOLUTIONS, INC.
- Current Assignee Address: US MA Woburn
- Agency: Lando & Anastasi, LLP
- Main IPC: H03H9/05
- IPC: H03H9/05 ; H03H9/10 ; H03H3/08
Abstract:
A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate.
Public/Granted literature
Information query
