Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology.