Invention Grant
- Patent Title: Semiconductor device package including filling mold via
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Application No.: US15362548Application Date: 2016-11-28
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Publication No.: US10381300B2Publication Date: 2019-08-13
- Inventor: Jen-Chieh Kao , Chang-Lin Yeh , Yi Chen , Sung-Hung Chiang
- Applicant: Advanced Semiconductor Engineering, Inc.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48 ; H01L23/02 ; H01L23/00 ; H01L23/552 ; H01L23/31 ; H01L23/538

Abstract:
A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.
Public/Granted literature
- US20180151485A1 SEMICONDUCTOR DEVICE PACKAGE INCLUDING FILLING MOLD VIA Public/Granted day:2018-05-31
Information query
IPC分类: