Invention Grant
- Patent Title: Semiconductor integrated circuit device
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Application No.: US15609535Application Date: 2017-05-31
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Publication No.: US10381827B2Publication Date: 2019-08-13
- Inventor: Mutsuo Nishikawa , Kazuhiro Matsunami , Katsuhiro Shimazu
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2016-120281 20160616
- Main IPC: H02H9/04
- IPC: H02H9/04 ; H01L23/528 ; H01L27/02 ; H01L27/06 ; H01L27/088 ; H03K19/003 ; H02H3/20 ; H02H11/00 ; H03K3/356 ; H01L21/8234

Abstract:
A protection circuit includes a first PMOS and a first PDMOS receiving input of voltage of a voltage dividing point of voltage input from an external power supply terminal, and a second PMOS and a second PDMOS receiving input of drain output voltage of the first PDMOS. The first PMOS is connected on the external power supply terminal side of the first PDMOS, and the second PMOS is connected on the external power supply terminal side of the second PDMOS. During overvoltage application, the voltage of the voltage dividing point is clamped to the breakdown voltage of a Zener diode, the second PDMOS turns OFF, and supply to an integrated circuit protected from overvoltage is cut off. When the voltage source is connected in reverse, parasitic diodes of the first and second PMOSs are reverse-biased and the flow of current in a path through the parasitic diodes is inhibited.
Public/Granted literature
- US20170366004A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2017-12-21
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